This invention relates to large capacity telecommunications switches constructed using a matrix (modular) architecture, and is particularly concerned with the provision of redundancy to provide a measure of protection against failure of the switch caused by failure of an individual component thereof.
Referring to FIG. 1, in one form of large capacity telecommunications switch, n smaller capacity switches, node switches, 10.1, 10.2 . . . 10.n, which are employed as buffers/time switches, on the periphery are connected to each other via an optical space switch core 11 which is functionally an n.times.n crosspoint. This core 11 may be implemented as a broadcast and select network arranged such that the incoming data streams from each of the n node switches 10 is first split n, ways, and then a selector mechanism (not shown) chooses which parts of the incoming data streams shall be onwardly directed to which node switch. The selector mechanism forms part of the core 11, and therefore, from the outside, the core appears as a crosspoint. The connections in the core 11 are re-arranged according to the traffic presented using a grant/request mechanism (not shown) under the control of core scheduler (not shown).
The arrangement of FIG. 1 can be re-drawn, as depicted in FIG. 2, to resemble a series of switches interconnected via a n-line bus 20. Each node switch 10.1, 10.2 . . . 10.n transmits on an associated line 20.1, 20.2 . . . 20.n of the bus, but can receive from any line. A selector 21.1, 21.2 . . . 21.n associated with each node switch determines which line is to be received by that node-switch at any given time. The switch of FIG. 2 is completely equivalent to that of FIG. 1, but suggests a different partitioning in which the selection of the required signal is performed at the node switch rather than in the core, which latter thus becomes a completely passive arrangement of optical waveguide splitters and connectors.
An n.times.m matrix arrangement of buffers and buses can be employed to make a large switch from an assembly of smaller units (nodes). The array may be square (n=m) or rectangular (n.noteq.m). In such an architecture, as depicted in FIG. 3, n.times.n nodes 30 are arranged in a square matrix. Each node 30 has an external input port 31, an external output port 32, and internal input and output ports connected to vertical and horizontal buses 33 and 34. A signal applied to the external input 31 port of any particular node 30 can be routed by the switch to the external output port of any other node by propagation along the buses 33 and 34 and through, in most instances, a sequence of three nodes. Thus a signal applied to the external input port of node A and destined for the external output port of node D can follow the route ABD or the route ACD. More complicated routes e.g. AEFD are also possible if, for instance, required because of failure of some component.
An individual node 30 of the switch of FIG. 3 may take the form illustrated in FIG. 4. This depicts the external input and output ports 31 and 32, and the vertical and horizontal buses 33 and 34 which convey data over lines 37a and 34a, and control signals over lines 33b and 34b, with request and grant control signals R, G to and from a traffic control 40. A buffer 41 process inputs from a multiplexer 42 and provides outputs to a demultiplexer 43. The multiplexer 42 has three inputs comprising the external input 31, an input from the vertical data bus 33a via a bus line selector 44, and an input from the horizontal data bus 34a via bus line selector 45. The demultiplexer similarly has three outputs comprising the external output 32 and inputs 46 and 47 respectively to the vertical and horizontal data buses 33a and 34a.
Reverting attention to FIG. 3, the input and output ports 31 and 32 of each of the n.times.n nodes will be connected to a peripheral (not shown) associated with that node. It is normal practice to provide dual fabrics for fault protection, which would imply that the n.times.n associated peripherals would be connected not only to the switch fabric of FIG. 3 in one plane, but also to a duplicate of that switch fabric in an adjacent plane. The peripherals would normally also be duplicated or for instance each of a set of line cards connected to the switch would be connected to two different peripherals. Now in these circumstances, if the switch were a 16.times.16 matrix, then there will be 256 nodes in one plane, and a further 256 nodes in the other plane. In the normal course of events the first plane matrix will be active while the second plane matrix remains redundant (inactive) until a fault occurs in the first plane matrix, and at this stage the second plane matrix is activated. It is most likely that no more than one node or one bus will fail at any one time, and so for the sake of a single node failure that leaves 255 still in working order, all these 255 nodes are disabled by the activation of the second plane matrix and the consequent closing down of the first plane matrix.